Conventionally, an electronic device uses a semiconductor apparatus mounted with a semiconductor package in which a plurality of solder ball electrodes are arranged in an array. At this time, a semiconductor device and package mold which form the semiconductor package, a printed circuit board, and the ball electrodes which bond the semiconductor package to the printed circuit board have different coefficients of thermal expansion. Hence, when heat is applied to the semiconductor apparatus, a large stress locally acts on the ball electrodes serving as a bonding portion to considerably shorten the service life of the bonding portion.
As a method of decreasing such a thermal stress, a technique is known in which reinforcing projections (bumps) are arranged in the vicinities of, among the ball electrodes arranged in an array, those at the outermost portion and innermost portion on which the largest stress acts (see Japanese Patent Laid-Open No. 9-162241 (FIGS. 2, 4, and 6 on pages 2 and 3)).
In recent years, as the mounting integration degree increases, semiconductor packages are often respectively mounted on the two surfaces of a printed circuit board. When the semiconductor packages are mounted on the two surfaces of the printed circuit board, one semiconductor package constrains deformation of the other semiconductor package, so that the printed circuit board cannot flex freely. Therefore, a larger stress acts on the solder bonding portion than in a case wherein a semiconductor package is mounted on only one surface of the printed circuit board, thus largely degrading the reliability.
In view of this, for mounting the semiconductor packages on the two surfaces of the printed circuit board, a method of decreasing the thermal stress of the ball electrodes is known. More specifically, this method comprises a technique of arranging the semiconductor packages respectively on the two surfaces of the printed circuit board such that the ball electrode portions of the semiconductor packages do not correspond to the same positions on the two surfaces of the printed circuit board (see Japanese Patent Laid-Open No. 5-82937 (FIGS. 1 to 3 on pages 3 and 4)).
Similarly, a method is also known of decreasing the warp of a printed circuit board having two surfaces where semiconductor package mold printed circuit boards are respectively mounted. More specifically, this method comprises a technique of respectively arranging plates each having openings on the two surfaces of a printed circuit board such that opposing frames overlap at least partially (see Japanese Patent Laid-Open No. 2001-326322 (FIGS. 1 and 2 on pages 5 and 6)).
According to the mounting method described in Japanese Patent Laid-Open No. 5-82937, the semiconductor devices are bonded at the lead portions such that the semiconductor packages to be mounted on the two surfaces of the circuit board are shifted from each other between the upper and lower surfaces. If, however, semiconductor packages each having ball electrodes arranged in an array are mounted on the two surfaces of a printed circuit board in the same manner as described above such that they are shifted from each other between the upper and lower surfaces, it causes very complicated thermal deformation, as will be described later. Accordingly, a very high stress locally acts to decrease the service life of specific ball electrodes. This shortens the service life as the semiconductor packages.
The mounting method described in Japanese Patent Laid-Open No. 9-162241 requires the reinforcing bumps, and the mounting method described in Japanese Patent Laid-Open No. 2001-326322 requires the additional reinforcing plates. Consequently, the manufacturing cost increases greatly, which is not realistic.